Hold your beathe as we present you one of the most interesting thing about Verilog, VHDL - the world of ASIC programming. We have been inspired by the
Verilog Tutorial , we we can shamelessly say is one of the most wonderful tutorial, ever made about verilog and VHDL.
Read on.
But today, it is time to read about Always and Initial block.
An always block contains procedural statements inside and models an abstract circuit part.
It is intended for synthesis. The block has a sensitivity list but contains no other explicit timing control constructs. Activation and execution of the always block are trigged by the designated events of the sensitivity list. For modeling purposes, an always block can contain timing constructs to specify the relevant propagation delays of various constructs or to wait for a specific event. The sensitivity list can sometimes be omitted. For example, we can use the following segment to model a clock signal, which alternates between 0 and 1 every 20 time units and runs forever.
always
begin
clk = l'bl;
#20;
clk = l'bO;
#20;
end
An initial block also contains procedural statements inside. However, it is executed only once at the beginning of simulation. The simplified syntax is
initial
begin
[procedural statements]
end
An initial block is frequently used to set the initial values of variables. In Listing 1.7, it is used to generate the entire testing sequence. The "run-once" behavior of an initial block usually cannot be synthesized.
Read on.
But today, it is time to read about Always and Initial block.
Always block and initial block
Basically Verilog HDL programming language has two and only two types of procedural blocks: an always block and a initial block. Let us take a look at the difference between these two.An always block contains procedural statements inside and models an abstract circuit part.
It is intended for synthesis. The block has a sensitivity list but contains no other explicit timing control constructs. Activation and execution of the always block are trigged by the designated events of the sensitivity list. For modeling purposes, an always block can contain timing constructs to specify the relevant propagation delays of various constructs or to wait for a specific event. The sensitivity list can sometimes be omitted. For example, we can use the following segment to model a clock signal, which alternates between 0 and 1 every 20 time units and runs forever.
always
begin
clk = l'bl;
#20;
clk = l'bO;
#20;
end
An initial block also contains procedural statements inside. However, it is executed only once at the beginning of simulation. The simplified syntax is
initial
begin
[procedural statements]
end
An initial block is frequently used to set the initial values of variables. In Listing 1.7, it is used to generate the entire testing sequence. The "run-once" behavior of an initial block usually cannot be synthesized.
